1. Field of the Invention:
This invention relates generally to operational amplifiers and, more particularly, to an operational amplifier having an output stage comprised of only NPN output transistors and providing a .beta..sup.3 current gain from the input of the second stage to an open collector output. Amplifier frequency stability is achieved by placing a stabilizing capacitor across the second stage which forms a feedback loop about the second stage which loop is itself frequency stabilized by a stabilizing network.
2. Description of the Prior Art:
Most prior art operational amplifiers comprise an input gain stage, usually of the differential comparator type, an output stage including NPN and PNP transistors coupled in a push-pull configuration, and a second gain stage coupled between the input and output stages. The second stage generally consists of a gain transistor preceded by a single follower transistor having a base coupled to the output of the input stage. As a result of the current gains of the second stage gain transistor, the preceding follower transistor, and the pull-up NPN or the pull-down PNP output transistors, a .beta..sup.3 current gain is achieved from the output of the input stage to the amplifier output. This substantially reduces base current loading on the input stage which, if unchecked, would cause the input stage offset voltage to shift with load current.
In order to achieve a higher frequency response, greater output swing, reduce output stage second order peaking with capacitive loads, and simplify integrated circuit construction, it is desirable to provide an operational amplifier second stage and output stage which incorporates only NPN transistors. In order to accomplish this, it is necessary that an NPN transistor with its emitter terminal which is connected to some potential (e.g. ground) and a collector terminal coupled to the load serve simultaneously as the second gain stage and the output pull down. Such a stage as is shown and described in co-pending application Ser. No. 244,411 now abandoned filed Mar. 16, 1981 and assigned to the assignee of the present invention. The incorporation of such an output stage in an operational amplifier still requires that precautions be taken to prevent unwanted base current loading on the input stage. The inclusion of a single emitter follower transistor between the input of the NPN output stage and the output of the input stage would not be sufficient to provide the necessary input stage current isolation from output load currents. However, the inclusion of additional current gain in the second stage will minimize loading at the output of the input stage. However, placing a stabilizing capacitor across the second stage will result in a parasitic second stage loop frequency instability.
U.S. Pat. No. 3,416,092 issued Dec. 10, 1968 and assigned to the assignee of the present invention describes an amplifier having an all NPN output stage including an NPN pull-down transistor also serving as a second gain stage and the necessary first and second NPN follower transistors connected between base of the pull-down transistor and the output of the amplifier's first stage. This patent suggests that a stabilizing capacitor be coupled between the collector of the pull-down transistor and the base of the follower transistor whose emitter supplies base current directly to the pull-down transistor. Unfortunately, this arrangement does not maximize amplifier gain due to additional excess phase shift in the remaining open loop circuit path not shunted or broadbanded by the stabilizing feedback capacitor.